The present invention relates to a dual gate of a semiconductor device and a method for manufacturing the same, and more particularly to a dual gate of a semiconductor device capable of forming a layer doped in a high concentration over a recessed portion of a semiconductor substrate when forming a dual gate having a recess channel structure and a method for manufacturing the same.
As is known in the art, a conductive layer of a gate of a MOSFET device is mainly made of a polysilicon layer. This is because the polysilicon layer displays the physical properties required for a gate such as a high melting point, ease of forming a thin film, ease of patterning a line, and stability in an oxidation atmosphere and formation of a planarized surface. In an actual MOSFET device, a polysilicon gate contains a dopant such as phosphorous (P), arsenic (As) and boron (B), thereby realizing a low resistance.
Also, a cell region, a NMOS area, and a PMOS area in a CMOS device are all formed with N+ polysilicon gates. In this case, the NMOS device has a surface channel, whereas the PMOS device has a buried channel by a count doping.
Meanwhile, as the integration level of semiconductor devices increases, the width of a gate electrode, e.g. a half-pitch of a gate, has decreased to less than 10 nm. The PMOS device, unlike the NMOS device having a surface channel, is therefore disadvantaged by an increase in a short channel effect due to the buried channel.
Accordingly, a dual gate forming method has been developed in which an N+ poly gate doped with phosphorous (P) is formed in the NMOS forming area and a P+ poly gate doped with boron (B) is formed in the PMOS forming area. In this dual gate forming method, both the NMOS and PMOS channels are surface channels, thereby eliminating the disadvantage created by a buried channel.
Hereafter, a method for forming a dual gate of a semiconductor device in accordance with the prior art will be briefly described.
A cell region of a semiconductor substrate that is divided into the cell region and a peripheral region including PMOS and NMOS forming areas to recess a gate forming area. A gate insulation layer is formed over the entire surface of the semiconductor substrate including the recessed portion. A polysilicon layer is deposited over the gate insulation layer. After P-type impurities are ion implanted into a portion of the polysilicon layer formed in the cell region and the PMOS forming area of the peripheral region to form a P+ polysilicon layer, N-type impurities are ion implanted into the NMOS forming area of the remainder peripheral region to form a N+ polysilicon layer.
After a metallic layer and a hard mask layer are sequentially formed over the P+ polysilicon layer and the N+ polysilicon layer, the hard mask layer, metallic layer, P+ polysilicon layer and the N+ polysilicon layer, and the gate insulation layer are etched to form a gate in each area of each region, thereby forming the dual gate.
However, in the prior art described above, the ion implantation of the P-type impurities is not implanted into the requisite portion of the polysilicon layer formed over the recessed portion of the cell region of the semiconductor substrate in a consistent manner. As a result, the upper end portion of the P+ polysilicon layer formed over the recessed portion of the semiconductor substrate has a high concentration of P-type impurities while the lower end portion of the P+ polysilicon layer has a low concentration of P-type impurities. The threshold voltage (Vt) of the gate formed in the cell region is therefore reduced, thereby compromising device characteristics and lowering reliability.
Meanwhile, in order to form the polysilicon layer doped in a high concentration over the recessed portion of the semiconductor substrate, there has been suggested a method of performing ion implantation of high dose P-type impurities. However, this method causes the refresh characteristic to be lowered because the electric field is increased and thus the leakage current is also increased. Further, using a high dosage when performing ion implantation of the P-type impurities increases the amount of penetrated impurity which subsequently changes the threshold voltage of the transistor, thereby lowering the reliability of the gate insulation layer.